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HC5526
Data Sheet October 1998 File Number 4151.6
ITU CO/PABX SLIC with Low Power Standby
The HC5526 is a subscriber line interface circuit that is compliant with CCITT standards. Enhancements include immunity to circuit latch-up during hot plug and absence of false signaling in the presence of longitudinal currents. The HC5526 is fabricated in a High Voltage Dielectrically Isolated (DI) Bipolar Process that eliminates leakage currents and device latch-up problems normally associated with Junction Isolated (JI) ICs. The elimination of the leakage currents results in improved circuit performance for wide temperature extremes. The latch free benefit of the DI process guarantees operation under adverse transient conditions. This process feature makes the HC5526 ideally suited for use in harsh outdoor environments.
Features
* DI Monolithic High Voltage Process * Programmable Current Feed (20mA to 60mA) * Programmable Loop Current Detector Threshold and Battery Feed Characteristics * Ground Key and Ring Trip Detection * Compatible with Ericsson's PBL3764 * Thermal Shutdown * On-Hook Transmission * Wide Battery Voltage Range (-24V to -58V) * Low Standby Power * Meets CCITT Transmission Requirements * -40oC to 85oC Ambient Temperature Range
PKG. NO. N28.45 E22.4 N28.45 E22.4
Ordering Information
PART NUMBER HC5526CM HC5526CP HC5526IM HC5526IP TEMP. RANGE (oC) 0 to 70 0 to 70 -40 to 85 -40 to 85 PACKAGE 28 Ld PLCC 22 Ld PDIP 28 Ld PLCC 22 Ld PDIP
Applications
* On-Premises (ONS) * Key Systems * PBX * Related Literature - AN9537, Operation of the HC5513/26 Evaluation Board
Block Diagram
RINGRLY RING RELAY DRIVER 4-WIRE INTERFACE VF SIGNAL PATH
VTX RSN
DT DR
RING TRIP DETECTOR
TIP RING HPT HPR GROUND KEY DETECTOR VBAT VCC VEE AGND BGND BIAS RD RDC RSG DET DIGITAL MULTIPLEXER
2-WIRE INTERFACE
LOOP CURRENT DETECTOR
E0 E1 C1 C2
57
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HC5526
Absolute Maximum Ratings
Operating Temperature Range . . . . . . . . . . . . . . . . -40oC to 110oC Power Supply (-40oC TA 85oC) Supply Voltage VCC to GND . . . . . . . . . . . . . . . . . . . . 0.5V to 7V Supply Voltage VEE to GND. . . . . . . . . . . . . . . . . . . . . -7V to 0.5V Supply Voltage VBAT to GND . . . . . . . . . . . . . . . . . . . -70V to 0.5V Ground Voltage between AGND and BGND . . . . . . . . . . . . . -0.3V to 0.3V Relay Driver Ring Relay Supply Voltage . . . . . . . . . . . . . . . . . 0V to VBAT 75V Ring Relay Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Ring Trip Comparator Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VBAT to 0V Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA to 5mA Digital Inputs, Outputs (C1, C2, E0, E1, DET) Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to VCC Output Voltage (DET Not Active) . . . . . . . . . . . . . . . . . 0V to VCC Output Current (DET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Tipx and Ringx Terminals (-40oC TA 85oC) Tipx or Ringx Voltage, Continuous (Referenced to GND) VBAT to 2V Tipx or Ringx, Pulse < 10ms, TREP > 10s . . . . . .VBAT -20V to 5V Tipx or Ringx, Pulse < 10s, TREP > 10s . . . . VBAT -40V to 10V Tipx or Ringx, Pulse < 250ns, TREP > 10s. . . . VBAT -70V to 15V Tipx or Ringx Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70mA ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) 22 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . . 53 28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . 53 Continuous Dissipation at 70oC 22 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5W 28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5W Package Power Dissipation at 70oC, t < 100ms, tREP > 1s 22 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4W 28 Lead PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4W Derate above . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70oC PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.8mW/oC PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.8mW/oC Maximum Junction Temperature Range. . . . . . . . . . -40oC to 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (PLCC - Lead Tips Only)
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . 543 Transistors, 51 Diodes
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Typical Operating Conditions
These represent the conditions under which the part was developed and are suggested as guidelines. PARAMETER Case Temperature VCC with Respect to AGND VEE with Respect to AGND VBAT with Respect to BGND 0oC to 70oC 0oC to 70oC 0oC to 70oC CONDITIONS MIN -40 4.75 -5.25 -58 TYP MAX 100 5.25 -4.75 -24 UNITS
oC
V V V
Electrical Specifications
TA = 0oC to 70oC, VCC = 5V 5%, VEE = -5V 5%, VBAT = -28V, AGND = BGND = 0V, RDC1 = RDC2 = 41.2k, RD = 39k, RSG = , RF1 = RF2 = 0, CHP = 10nF, CDC = 1.5F, ZL = 600, Unless Otherwise Specified. All pin number references in the figures refer to the 28 lead PLCC package. CONDITIONS 1% THD, ZL = 600, (Note 2, Figure 1) 0 < f < 100Hz (Note 3, Figure 2) MIN 3.1 TYP 20 MAX 35 UNITS VPEAK /Wire
PARAMETER Overload Level Longitudinal Impedance (Tip/Ring)
1VRMS TIP 27 RL 600 IDCMET 23mA RING 28 RSN 16 VTX 19 RT 600k ERX 0 < f < 100Hz EL C 2.16F 300 300
AT VT
TIP 27
VTX 19 RT 600k
VTRO
VR AR RING 28 RSN 16
RRX 300k LZR = VR/AR
RRX 300k
LZT = VT/AT
FIGURE 1. OVERLOAD LEVEL (TWO-WIRE PORT)
FIGURE 2. LONGITUDINAL IMPEDANCE
58
HC5526
Electrical Specifications
TA = 0oC to 70oC, VCC = 5V 5%, VEE = -5V 5%, VBAT = -28V, AGND = BGND = 0V, RDC1 = RDC2 = 41.2k, RD = 39k, RSG = , RF1 = RF2 = 0, CHP = 10nF, CDC = 1.5F, ZL = 600, Unless Otherwise Specified. All pin number references in the figures refer to the 28 lead PLCC package. (Continued) CONDITIONS MIN TYP MAX UNITS
PARAMETER LONGITUDINAL CURRENT LIMIT (TIP/RING) Off-Hook (Active) On-Hook (Standby), RL =
No False Detections (Loop Current), LB > 45dB (Note 4, Figure 3A) No False Detections (Loop Current) (Note 5, Figure 3B)
-
-
20 5
mAPEAK/Wire
mAPEAK/Wire
368 A C EL 2.16F -5V RDC2 A 368 RING RDC 28 14 41.2k DET 39k RD RDC1 41.2k CDC 1.5F TIP 27 RSN 16 2.16F EL 2.16F
368 A C 39k RD -5V C A 368 RDC2 RDC RING 14 41.2k 28 DET TIP 27 RSN 16 RDC1 41.2k CDC 1.5F
FIGURE 3A. OFF-HOOK FIGURE 3. LONGITUDINAL CURRENT LIMIT OFF-HOOK LONGITUDINAL BALANCE Longitudinal to Metallic Longitudinal to Metallic Metallic to Longitudinal IEEE 455 - 1985, RLR, RLT = 368, 0.2kHz < f < 4.0kHz (Note 6, Figure 4) RLR, RLT = 300, 0.2kHz < f < 4.0kHz (Note 6, Figure 4) FCC Part 68, Para 68.310 0.2kHz < f < 1.0kHz 1.0kHz < f < 4.0kHz (Note 7) Longitudinal to 4-Wire Metallic to Longitudinal 4-Wire to Longitudinal 0.2kHz < f < 4.0kHz (Note 8, Figure 4) RLR , RLT = 300, 0.2kHz < f < 4.0kHz (Note 9, Figure 5) 0.2kHz < f < 4.0kHz (Note 10, Figure 5)
FIGURE 3B. ON-HOOK
53 53 50 50 53 50 50
60 60 55 55 60 55 55
-
dB dB dB dB dB dB dB
RLT TIP 27 EL C VTR 2.16F RRX RLR RING 28 RSN 16 300k VTX 19 RT 600k VTX VL 2.16F C
RLT 300 ETR TIP 27 VTX 19 RT 600k RRX RING 28 RSN 16 300k ERX
RLR 300
FIGURE 4. LONGITUDINAL TO METALLIC AND LONGITUDINAL TO 4-WIRE BALANCE 2-Wire Return Loss CHP = 20nF
FIGURE 5. METALLIC TO LONGITUDINAL AND 4-WIRE TO LONGITUDINAL BALANCE 25 27 23 dB dB dB
0.2kHz to 0.5kHz (Note 11, Figure 6) 0.5kHz to 1.0kHz (Note 11, Figure 6) 1.0kHz to 3.4kHz (Note 11, Figure 6)
59
HC5526
Electrical Specifications
TA = 0oC to 70oC, VCC = 5V 5%, VEE = -5V 5%, VBAT = -28V, AGND = BGND = 0V, RDC1 = RDC2 = 41.2k, RD = 39k, RSG = , RF1 = RF2 = 0, CHP = 10nF, CDC = 1.5F, ZL = 600, Unless Otherwise Specified. All pin number references in the figures refer to the 28 lead PLCC package. (Continued) CONDITIONS MIN TYP MAX UNITS
PARAMETER TIP IDLE VOLTAGE Active, IL = 0 Standby, IL = 0 RING IDLE VOLTAGE Active, IL = 0 Standby, IL = 0 4-WIRE TRANSMIT PORT (VTX) Overload Level Output Offset Voltage Output Impedance (Guaranteed by Design) 2- to 4-Wire (Metallic to VTX) Voltage Gain
ZD TIP 27 R VS R ZIN RING 28 RSN 16 VM RT 600k VTX 19
-
-4 <0
-
V V
-
-24 >-28
-
V V
ZL > 20k, 1% THD (Note 12, Figure 7) EG = 0, ZL = (Note 13, Figure 7) 0.2kHz < f < 03.4kHz 0.3kHz < f < 03.4kHz (Note 14, Figure 7)
2.16F RL 600 C VTR IDCMET 23mA
3.1 -60 0.98
TIP 27
5 1.0
VTX 19
60 20 1.02
VPEAK mV V/V
RT 600k
EG RRX 300k
VTXO VTX
ZL
RRX RING 28 RSN 16 300k
RLR
FIGURE 6. TWO-WIRE RETURN LOSS
FIGURE 7. OVERLOAD LEVEL (4-WIRE TRANSMIT PORT), OUTPUT OFFSET VOLTAGE, 2-WIRE TO 4-WIRE VOLTAGE GAIN AND HARMONIC DISTORTION
4-WIRE RECEIVE PORT (RSN) DC Voltage RX Sum Node Impedance (Guaranteed by Design) Current Gain-RSN to Metallic FREQUENCY RESPONSE (OFF-HOOK) 2-Wire to 4-Wire 4-Wire to 2-Wire 4-Wire to 4-Wire INSERTION LOSS 2-Wire to 4-Wire 4-Wire to 2-Wire GAIN TRACKING (Ref = -10dBm, at 1.0kHz) 2-Wire to 4-Wire 2-Wire to 4-Wire 4-Wire to 2-Wire -40dBm to +3dBm (Note 21, Figure 9) -55dBm to -40dBm (Note 21, Figure 9) -40dBm to +3dBm (Note 22, Figure 9) -0.1 -0.1 0.03 0.1 0.1 dB dB dB 0dBm, 1kHz (Note 19, Figure 9) 0dBm, 1kHz (Note 20, Figure 9) -0.2 -0.2 0.2 0.2 dB dB 0dBm at 1.0kHz, ERX = 0V, 0.3kHz < f < 3.4kHz (Note 16, Figure 9) 0dBm at 1.0kHz, EG = 0V, 0.3kHz < f < 3.4kHz (Note 17, Figure 9) 0dBm at 1.0kHz, EG = 0V, 0.3kHz < f < 3.4kHz (Note 18, Figure 9) -0.2 -0.2 -0.2 0.2 0.2 0.2 dB dB dB IRSN = 0mA 0.3kHz < f < 3.4kHz 0.3kHz < f < 3.4kHz (Note 15, Figure 8) 980 0 1000 20 1020 V Ratio
60
HC5526
Electrical Specifications
TA = 0oC to 70oC, VCC = 5V 5%, VEE = -5V 5%, VBAT = -28V, AGND = BGND = 0V, RDC1 = RDC2 = 41.2k, RD = 39k, RSG = , RF1 = RF2 = 0, CHP = 10nF, CDC = 1.5F, ZL = 600, Unless Otherwise Specified. All pin number references in the figures refer to the 28 lead PLCC package. (Continued) CONDITIONS -55dBm to -40dBm (Note 22, Figure 9) MIN TYP 0.03 MAX UNITS dB
PARAMETER 4-Wire to 2-Wire GRX = ((VTR1- VTR2)(300k))/(-3)(600)
Where: VTR1 is the Tip to Ring Voltage with VRSN = 0V and VTR2 is the Tip to Ring Voltage with VRSN = -3V VRSN = 0V
RRX TIP 27 RL 600 RSN 16 300k RDC1 41.2k VRSN = -3V RL 600
C TIP 27 VTX 19 RT 600k VTR RRX VTX ERX
IDCMET EG 1/C << RL
VTR
RDC2 RING 28 RDC 14 41.2k
CDC 1.5F
RING 28
RSN 16
300k
FIGURE 8. CURRENT GAIN-RSN TO METALLIC NOISE Idle Channel Noise at 2-Wire Idle Channel Noise at 4-Wire HARMONIC DISTORTION 2-Wire to 4-Wire 4-Wire to 2-Wire BATTERY FEED CHARACTERISTICS Constant Loop Current Tolerance RDCX = 41.2k Loop Current Tolerance (Standby) Open Circuit Voltage (VTIP - VRING) LOOP CURRENT DETECTOR On-Hook to Off-Hook Off-Hook to On-Hook Loop Current Hysteresis GROUND KEY DETECTOR Tip/Ring Current Difference - Trigger Tip/Ring Current Difference - Reset (Note 29, Figure 11) (Note 29, Figure 11) RD = 39k, 0oC to 70oC RD = 39k, 0oC to 70oC RD = 39k, 0oC to 70oC IL = 2500/(RDC1 + RDC2), 0oC to 70oC (Note 27) IL = (VBAT-3)/(RL +1800), 0oC to 70oC (Note 28) 0oC to 70oC, (Active)
FIGURE 9. FREQUENCY RESPONSE, INSERTION LOSS, GAIN TRACKING AND HARMONIC DISTORTION
C-Message Weighting (Note 23, Figure 10) C-Message Weighting (Note 24, Figure 10)
-
10 10
-
dBrnC dBrnC
0dBm, 1kHz (Note 25, Figure 7) 0dBm, 0.3kHz to 3.4kHz (Note 26, Figure 9)
-
-65 -65
-54 -54
dB dB
0.9IL 0.8IL 14
IL IL -
1.1IL 1.2IL 20
mA mA V
372/RD 325/RD 25/RD
465/RD 405/RD 60/RD
558/RD 485/RD 95/RD
mA mA mA
8 3
12 7
17 12
mA mA
61
HC5526
Electrical Specifications
TA = 0oC to 70oC, VCC = 5V 5%, VEE = -5V 5%, VBAT = -28V, AGND = BGND = 0V, RDC1 = RDC2 = 41.2k, RD = 39k, RSG = , RF1 = RF2 = 0, CHP = 10nF, CDC = 1.5F, ZL = 600, Unless Otherwise Specified. All pin number references in the figures refer to the 28 lead PLCC package. (Continued) CONDITIONS (Note 29, Figure 11) MIN 0 TYP 5 MAX 9 UNITS mA
PARAMETER Hysteresis
TIP 27 RL 600
VTX 19 RT 600k
TIP 27
RSN 16 RDC1 41.2k
VTR
VTX RDC2 RING RDC 28 DET 14 41.2k CDC 1.5F
RRX RING 28 RSN 16 300k
E1 = C1 = 0, C2 = 1
FIGURE 10. IDLE CHANNEL NOISE RING TRIP DETECTOR (DT, DR) Offset Voltage Input Bias Current Input Common-Mode Range Input Resistance RING RELAY DRIVER VSAT at 25mA Off-State Leakage Current DIGITAL INPUTS (E0, E1, C1, C2) Input Low Voltage, VIL Input High Voltage, VIH Input Low Current, IIL: C1, C2 Input Low Current, IIL: E0, E1 Input High Current DETECTOR OUTPUT (DET) Output Low Voltage, VOL Output High Voltage, VOH Internal Pull-Up Resistor POWER DISSIPATION Open Circuit State On-Hook, Standby On-Hook, Active Off-Hook, Active C1 = C2 = 0 C1 = C2 = 1 C1 = 0, C2 = 1, RL = High Impedance RL = 0 RL = 300 RL = 600 TEMPERATURE GUARD Thermal Shutdown IOL = 2mA IOH = 100A VIL = 0.4V VIL = 0.4V VIH = 2.4V IOL = 25mA VOH = 12V Source Res = 0 Source Res = 0 Source Res = 0 Source Res = 0, Balanced
FIGURE 11. GROUND KEY DETECT
-20 -500 VBAT +1 3
-
20 500 0 -
mV nA V M
-
1.0 -
1.5 10
V
A
0 2 -200 -100 -
-
0.8 VCC 40
V V A A A
2.7 10
15
0.45 20
V V k
-
-
23 30 150 1.1 0.75 0.5
mW mW mW W W W
150
-
180
oC
62
HC5526
Electrical Specifications
TA = 0oC to 70oC, VCC = 5V 5%, VEE = -5V 5%, VBAT = -28V, AGND = BGND = 0V, RDC1 = RDC2 = 41.2k, RD = 39k, RSG = , RF1 = RF2 = 0, CHP = 10nF, CDC = 1.5F, ZL = 600, Unless Otherwise Specified. All pin number references in the figures refer to the 28 lead PLCC package. (Continued) CONDITIONS MIN TYP MAX UNITS
PARAMETER SUPPLY CURRENTS (VBAT = -28V) ICC, On-Hook
Open Circuit State (C1, 2 = 0, 0) Standby State (C1, 2 = 1, 1) Active State (C1, 2 = 0,1)
-
-
1.5 1.7 5.5 0.8 0.8 2.2 0.4 0.6 3.9
mA mA mA mA mA mA mA mA mA
IEE, On-Hook
Open Circuit State (C1, 2 = 0, 0) Standby State (C1, 2 = 1, 1) Active State (C1, 2 = 0, 1)
IBAT, On-Hook
Open Circuit State (C1, 2 = 0, 0) Standby State (C1, 2 = 1, 1) Active State (C1, 2 = 0, 1)
PSRR VCC to 2 or 4-Wire Port VEE to 2 or 4-Wire Port VBAT to 2 or 4-Wire Port (Note 30, Figure 12) (Note 30, Figure 12) (Note 30, Figure 12) 40 40 40 dB dB dB
-48V SUPPLY 5V SUPPLY -5V SUPPLY TIP 27 RL 600
100mVRMS, 50Hz TO 4kHz
VTX 19 RT 600k VTX
PSRR = 20 log (VT X/VIN)
RRX RING 28 RSN 16 300k
FIGURE 12. POWER SUPPLY REJECTION RATIO
Circuit Operation and Design Information
The HC5526 is a current feed voltage sense Subscriber Line Interface Circuit (SLIC). This means that for short loop applications the SLIC provides a programmed constant current to the tip and ring terminals while sensing the tip to ring voltage. The following discussion separates the SLIC's operation into its DC and AC paths, then follows up with additional circuit and design information. the RDC pin (Figure 13). The RDC voltage is determined by the voltage across R1 in the saturation guard circuit. Under constant current feed conditions, the voltage drop across R1 sets the RDC voltage to -2.5V. This occurs when current flows through R1 into the current source I2 . The RDC voltage establishes a current (IRSN) that is equal to VRDC/(RDC1 +RDC2). This current is then multiplied by 1000, in the loop current circuit, to become the tip and ring loop currents. For the purpose of the following discussion, the saturation guard voltage is defined as the maximum tip to ring voltage at which the SLIC can provide a constant current for a given battery and overhead voltage.
Constant Loop Current (DC) Path
SLIC in the Active Mode
The DC path establishes a constant loop current that flows out of tip and into the ring terminal. The loop current is programmed by resistors RDC1 , RDC2 and the voltage on
63
HC5526
VTX + ITIP
-
TIP ITIP RING IRING
LOOP CURRENT CIRCUIT
IRSN
RSN
RRX
RDC1 CDC
IRING
+
RDC SATURATION GUARD CIRCUIT A2 I2 -5V -5V
RDC2
+ R1
-2.5V
A1 I1
+
-
RSG RSG -5V
HC5526
FIGURE 13. DC LOOP CURRENT
For loop resistances that result in a tip to ring voltage less than the saturation guard voltage the loop current is defined as:
2.5V I L = ------------------------------------- x 1000 R DC1 + R DC2 (EQ. 1)
where: IL = Constant loop current. RDC1 and RDC2 = Loop current programming resistors. Capacitor CDC between RDC1 and RDC2 removes the VF signals from the battery feed control loop. The value of CDC is determined by Equation 2:
1 1 C DC = T x --------------- + --------------- R R
DC1 DC2
Figure 15 shows the relationship between the saturation guard voltage, the loop current and the loop resistance. Notice from Figure 15 that for a loop resistance <1.2k (RSG = 21.4k) the SLIC is operating in the constant current feed region and for resistances >1.2k the SLIC is operating in the resistive feed region. Operation in the resistive feed region allows long loop and off-hook transmission by keeping the tip and ring voltages off the rails. Operation in this region is transparent to the customer.
50 TIP TO RING VOLTAGE (V) VBAT = -48V, RSG = 21.4k 40 30 20 10 0 VBAT = -24V, RSG = RESISTIVE FEED REGION 0 10 20 30 LOOP CURRENT (mA) 2k 700 <1.2k <400 RRSG = 21.4k RRSG = SATURATION GUARD VOLTAGE, VTR = 13V CONSTANT CURRENT FEED REGION SATURATION GUARD VOLTAGE, VTR = 38V
(EQ. 2)
where T = 30ms. The minimum CDC value is obtained if RDC1 = RDC2 . Figure 14 illustrates the relationship between the tip to ring voltage and the loop resistance. For a 0 loop resistance both tip and ring are at VBAT/2. As the loop resistance increases, so does the voltage differential between tip and ring. When this differential voltage becomes equal to the saturation guard voltage, the operation of the SLIC's loop feed changes from a constant current feed to a resistive feed. The loop current in the resistive feed region is no longer constant but varies as a function of the loop resistance.
0 TIP TO RING VOLTAGE (V) VBAT = -48V, IL = 23mA, RSG = 21.4k SATURATION GUARD VOLTAGE CONSTANT CURRENT FEED REGION RESISTIVE FEED REGION VTIP
RL RL
100k 100k
4k 1.5k
FIGURE 15. VTR vs IL and RL
-10
-20
-30
-40 SATURATION GUARD VOLTAGE 0 1.2K LOOP RESISTANCE () VRING
-50
FIGURE 14. VTR vs RL
The Saturation Guard circuit (Figure 13) monitors the tip to ring voltage via the transconductance amplifier A1. A1 generates a current that is proportional to the tip to ring voltage difference. I1 is internally set to sink all of A1's current until the tip to ring voltage exceeds 12.5V. When the tip to ring voltage exceeds 12.5V (with no RSG resistor) A1 supplies more current than I1 can sink. When this happens A2 amplifies its input current by a factor of 12 and the current through R1 becomes the difference between I2 and the output current from A2. As the current from A2 increases, the voltage across R1 decreases and the output voltage on RDC decreases. This results in a corresponding decrease in the loop current. The RSG pin provides the ability to increase the saturation guard reference voltage beyond 12.5V. Equation 3
64
HC5526
gives the relationship between the RSG resistor value and the programmable saturation guard reference voltage:
5 * 10 V SGREF = 12.5 + -----------------R SG
5
where: IL = Loop current in the standby state, RL = Loop resistance, and VBAT = Battery voltage.
(EQ. 3)
where: VSGREF = Saturation Guard reference voltage, and RSG = Saturation Guard programming resistor. When the Saturation guard reference voltage is exceeded, the tip to ring voltage is calculated using Equation 4:
16.66 + 5 * 10 R SG V TR = R L x ---------------------------------------------------------------------R L + ( R DC1 + R DC2 ) 600
5
(AC) Transmission Path
SLIC in the Active Mode
Figure 16 shows a simplified AC transmission model. Circuit analysis yields the following design equations:
V TR = V TX + I M * 2R F (EQ. 4) V TX V RX IM ---------- + ----------- = -----------Z T Z RX 1000 V TR = E G - I M * Z L (EQ. 10) (EQ. 9)
where: VTR = Voltage differential between tip and ring, and RL = Loop resistance. For on-hook transmission RL = , Equation 4 reduces to:
5 * 10 V TR = 16.66 + -----------------R SG
5
(EQ. 11)
where: VTR = Is the AC metallic voltage between tip and ring, including the voltage drop across the fuse resistors RF, VTX = Is the AC metallic voltage. Either at the ground referenced 4-wire side or the SLIC tip and ring terminals, IM = Is the AC metallic current, RF = Is a fuse resisto, ZT = Is used to set the SLIC's 2-wire impedance, VRX = Is the analog ground referenced receive signal, ZRX = Is used to set the 4-wire to 2-wire gain, EG = Is the AC open circuit voltage, and ZL = Is the line impedance.
(EQ. 5)
The value of RSG should be calculated to allow maximum loop length operation. This requires that the saturation guard reference voltage be set as high as possible without clipping the incoming or outgoing VF signal. A voltage margin of -4V on tip and -4V on ring, for a total of -8V margin, is recommended as a general guideline. The value of RSG is calculated using Equation 6:
5 * 10 R SG = ------------------------------------------------------------------------------------------------------------------------------------------------( R DC1 + R DC2 ) ( V BAT - V MARGIN ) x 1 + ------------------------------------------ - 16.66V 600R L (EQ. 6)
5
(AC) 2-Wire Impedance
The AC 2-wire impedance (ZTR) is the impedance looking into the SLIC, including the fuse resistors, and is calculated as follows: Let VRX = 0. Then from Equation 10:
IM V TX = Z T * -----------1000 (EQ. 12)
where: VBAT = Battery voltage, and VMARGIN = Recommended value of -8V to allow a maximum overload level of 3.1VPEAK . For on-hook transmission RL = , Equation 6 reduces to:
5 * 10 R SG = ---------------------------------------------------------------------------V BAT - V MARGIN - 16.66V
5
(EQ. 7)
ZTR is defined as:
V TR Z TR = ---------IM (EQ. 13)
SLIC in the Standby Mode
Overall system power is saved by configuring the SLIC in the standby state when not in use. In the standby state the tip and ring amplifiers are disabled and internal resistors are connected between tip to ground and ring to VBAT. This connection enables a loop current to flow when the phone goes off-hook. The loop current detector then detects this current and the SLIC is configured in the active mode for voice transmission. The loop current in standby state is calculated as follows:
V BAT - 3V I L ------------------------------R L + 1800 (EQ. 8)
Substituting in Equation 9 for VTR:
V TX 2R F * I M Z TR = ---------- + ---------------------IM IM (EQ. 14)
Substituting in Equation 12 for VTX:
ZT Z TR = ------------ + 2R F 1000 (EQ. 15)
65
HC5526
IM TIP A = 250 RF ZL ZTR + + + VTX VTX 1 + VTX ZT IM A = 250 RING RF IM 1000 A=4
VTR
+
-
EG
-
-
RSN
ZRX + VRX
HC5526
FIGURE 16. SIMPLIFIED AC TRANSMISSION CIRCUIT
-
Therefore:
Z T = 1000 * ( Z TR - 2R F ) (EQ. 16)
(AC) 4-Wire to 4-Wire Gain
The 4-wire to 4-wire gain is equal to VTX/VRX . From Equations 9, 10 and 11 with EG = 0:
Z L + 2R F V TX ZT A 4 - 4 = ----------- = - ---------- * ------------------------------------------ZT V RX Z RX ------------ + 2R F + Z L 1000 (EQ. 20)
Equation 16 can now be used to match the SLIC's impedance to any known line impedance (ZTR).
Example:
Calculate ZT to make ZTR = 600 in series with 2.16F. RF = 20.
1 Z T = 1000 * 600 + ----------------------------------------- - 2 * 20 -6 j * 2.16 * 10
Transhybrid Circuit
The purpose of the transhybrid circuit is to remove the receive signal (VRX) from the transmit signal (VTX), thereby preventing an echo on the transmit side. This is accomplished by using an external op amp (usually part of the CODEC) and by the inversion of the signal from the 4-wire receive port (RSN) to the 4-wire transmit port (VTX). Figure 17 shows the transhybrid circuit. The input signal will be subtracted from the output signal if I1 equals I2 . Node analysis yields the following equation:
V TX V RX ---------- + ----------- = 0 R TX Z B (EQ. 21)
ZT = 560k in series with 2.16nF.
(AC) 2-Wire to 4-Wire Gain
The 2-wire to 4-wire gain is equal to VTX/ VTR . From Equations 9 and 10 with VRX = 0:
Z T 1000 V TX A 2 - 4 = ---------- = ----------------------------------------V TR Z T 1000 + 2R F (EQ. 17)
(AC) 4-Wire to 2-Wire Gain
The 4-wire to 2-wire gain is equal to VTR/VRX . From Equations 9, 10 and 11 with EG = 0: For applications where the 2-wire impedance (ZTR ,
ZL V TR ZT A 4 - 2 = ----------- = - ---------- * ------------------------------------------ZT V RX Z RX ------------ + 2R F + Z L 1000 (EQ. 18)
The value of ZB is then:
V RX Z B = - R TX * ----------V
TX
(EQ. 22)
Where VRX/VTX equals 1/ A4-4 . Therefore:
ZT Z RX ------------ + 2R F + Z L 1000 Z B = R TX * ---------- * ------------------------------------------ZT Z L + 2R F (EQ. 23)
Equation 15) is chosen to equal the line impedance (ZL), the expression for A4-2 simplifies to:
ZT 1 A 4 - 2 = - ---------- * --Z RX 2 (EQ. 19)
Example:
Given: RTX = 20k, ZRX = 280k, ZT = 562k (standard value), RF = 20 and ZL = 600. The value of ZB = 18.7k.
66
HC5526
RFB I2 VTX RTX + I1 + VTX
voltage drop across RD exceeds 1.25V, and the logic is configured for loop current detection, the DET pin goes low. The hysteresis resistor RH adds an additional voltage effectively across RD, causing the on-hook to off-hook threshold to be slightly higher than the off-hook to on-hook threshold. Taking into account the hysteresis voltage, the typical value of RD for the on-hook to off-hook condition is:
-
HC5526
ZT
ZB + VRX
RSN ZRX
-
465 R D = ------------------------------------------------------------------------I ON - HOOK to OFF - HOOK
(EQ. 25)
CODEC/ FILTER
FIGURE 17. TRANSHYBRID CIRCUIT
Taking into account the hysteresis voltage, the typical value of RD for the off-hook to on-hook condition is:
375 R D = ------------------------------------------------------------------------I OFF - HOOK to ON - HOOK (EQ. 26)
Supervisory Functions
The loop current, ground key and the ring trip detector outputs are multiplexed to a single logic output pin called DET. See Table 1 to determine the active detector for a given logic input. For further discussion of the logic circuitry see section titled "Digital Logic Inputs". Before proceeding with an explanation of the loop current detector, ground key detector and later the longitudinal impedance, it is important to understand the difference between a "metallic" and "longitudinal" loop currents. Figure 18 illustrates 3 different types of loop current encountered. Case 1 illustrates the metallic loop current. The definition of a metallic loop current is when equal currents flow out of tip and into ring. Loop current is a metallic current. Cases 2 and 3 illustrate the longitudinal loop current. The definition of a longitudinal loop current is a common mode current, that flows either out of or into tip and ring simultaneously. Longitudinal currents in the on-hook state result in equal currents flowing through the sense resistors R1 and R2 (Figure 18). And longitudinal currents in the offhook state result in unequal currents flowing through the sense resistors R1 and R2 . Notice that for case 2, longitudinal currents flowing away from the SLIC, the current through R1 is the metallic loop current plus the longitudinal current; whereas the current through R2 is the metallic loop current minus the longitudinal current. Longitudinal currents are generated when the phone line is influenced by magnetic fields (e.g., power lines).
A filter capacitor (CD) in parallel with RD will improve the accuracy of the trip point in a noisy environment. The value of this capacitor is calculated using the following Equation:
T C D = ------RD (EQ. 27)
where: T = 0.5ms.
Ground Key Detector
A simplified schematic of the ground key detector is shown in Figure 18. Ground key, is the process in which the ring terminal is shorted to ground for the purpose of signaling an Operator or seizing a phone line (between the Central Office and a Private Branch Exchange). The Ground Key detector is activated when unequal current flow through resistors R1 and R2 . This results in a current (IGK) out of the transconductance amplifier (gm2) that is equal to the product of gm2 and the differential (ITIP -IRING) loop current. If IGK is less than the internal current source (I1), then diode D1 is on and the output of the ground key comparator is low. If IGK is greater than the internal current source (I1), then diode D2 is on and the output of the ground key comparator is high. With the output of the ground key comparator high, and the logic configured for ground key detect, the DET pin goes low. The ground key detector has a built in hysteresis of typically 5mA between its trigger and reset values.
Ring Trip Detector
Ring trip detection is accomplished with the internal ring trip comparator and the external circuitry shown in Figure 19. The process of ring trip is initiated when the logic input pins are in the following states: E0 = 0, E1 = 1/0, C1 = 1 and C2 = 0. This logic condition connects the ring trip comparator to the DET output, and causes the Ringrly pin to energize the ring relay. The ring relay connects the tip and ring of the phone to the external circuitry in Figure 19. When the phone is on-hook the DT pin is more positive than the DR pin and the DET output is high. For off-hook conditions DR is more positive than DT and DET goes low. When DET goes low, indicating that the phone has gone off-hook, the SLIC is commanded by the logic inputs to go into the active state. In the active state, tip and ring are once again connected to the phone and normal operation ensues.
Loop Current Detector
Figure 18 shows a simplified schematic of the loop current and ground key detectors. The loop current detector works by sensing the metallic current flowing through resistors R1 and R2 . This results in a current (IRD) out of the transconductance amplifier (gm1) that is equal to the product of gm1 and the metallic loop current. IRD then flows out the RD pin and through resistor RD to VEE . The value of IRD is equal to:
IL I TIP - I RING I RD = ----------------------------------- = --------600 300 (EQ. 24)
The IRD current results in a voltage drop across RD that is compared to an internal 1.25V reference voltage. When the
67
HC5526
gm1(IMETALLIC) RH CURRENT LOOP COMPARATOR gm1 gm2 R2 RING RH + + GROUND KEY COMPARATOR IGK gm2(ITIP - IRING) IRD + + RD CD
RD
+
-
-
TIP R1
VREF 1.25V
VEE -5V
CASE 1
IMETALLIC
CASE 2
ILONGITUDINAL
CASE 3
ILONGITUDINAL
-
-
D2 D1 I1
DIGITAL MULTIPLEXER
DET
HC5526
FIGURE 18. LOOP CURRENT AND GROUND KEY DETECTORS
Figure 19 illustrates battery backed unbalanced ring injected ringing. For tip injected ringing just reverse the leads to the phone. The ringing source could also be balanced.
NOTE: The DET output will toggle at 20Hz because the DT input is not completely filtered by CRT. Software can examine the duty cycle and determine if the DET pin is low for more that half the time, if so the off-hook condition is indicated.
CRT
amplifiers GT and GR accomplish this by sourcing or sinking the required current to maintain VC at VBAT/2. When a longitudinal current is injected onto the tip and ring inputs, the voltage at VC moves from it's equilibrium value VBAT/2. When VC changes by the amount VC, this change appears between the input terminals of the differential transconductance amplifiers GT and GR. The output of GT and GR are the differential currents I1 and I2, which in turn feed the differential inputs of current sources IT and IR respectively. IT and IR have current gains of 250 single ended and 500 differentially, thus leading to a change in IT and IR that is equal to 500(I) and 500(I2). The circuit shown in Figure 20(B) illustrates the tip side of the longitudinal network. The advantages of a differential input current source are: improved noise since the noise due to current source 2IO is now correlated, power savings due to differential current gain and minimized offset error at the Operational Amplifier inputs via the two 5k resistors.
RRT
R3
R1
DT + DR
-
DET
R4 TIP ERG R2
RING TRIP COMPARATOR
VBAT RING RING RELAY RINGRLY
HC5526
Digital Logic Inputs
Table 1 is the logic truth table for the TTL compatible logic input pins. The HC5526 has two enable inputs pins (E0, E1) and two control inputs pins (C1, C2). The enable pin E0 is used to enable or disable the DET output pin. The DET pin is enabled if E0 is at a logic level 0 and disabled if E0 is at a logic level 1. The enable pin E1 gates the ground key detector to the DET output with a logic level 0, and gates the loop or ring trip detector to the DET output with a logic level 1. A combination of the control pins C1 and C2 is used to select 1 of the 4 possible operating states. A description of each operating state and the control logic follow:
FIGURE 19. RING TRIP CIRCUIT FOR BATTERY BACKED RINGING
Longitudinal Impedance
The feedback loop described in Figure 20(A, B) realizes the desired longitudinal impedances from tip to ground and from ring to ground. Nominal longitudinal impedance is resistive and in the order of 22. In the presence of longitudinal currents this circuit attenuates the voltages that would otherwise appear at the tip and ring terminals, to levels well within the common mode range of the SLIC. In fact, longitudinal currents may exceed the programmed DC loop current without disturbing the SLIC's VF transmission capabilities. The function of this circuit is to maintain the tip and ring voltages symmetrically around VBAT/2, in the presence of longitudinal currents. The differential transconductance
Open Circuit State (C1 = 0, C2 = 0)
In this state the SLIC is effectively off. All detectors and both the tip and ring line drive amplifiers are powered down, presenting a high impedance to the line. Power dissipation is at a minimum.
68
HC5526
ILONG TIP CURRENT SOURCE WITH DIFFERENTIAL INPUTS 20 I1 GT RLARGE VC + VBAT/2 VC GR ILONG + VR RLARGE I2 RING IR I2 RLARGE GT RING TIP DIFFERENTIAL TRANSCONDUCTANCE AMPLIFIER 2I0 I1 I1 TIP 5k RLARGE 5k +
ILONG TIP + VT I1
IT
-
-
-
VBAT/2
ILONG
-
HC5526
FIGURE 20A. FIGURE 20. LONGITUDINAL IMPEDANCE NETWORK
FIGURE 20B.
Active State (C1 = 0, C2 = 1)
The tip output is capable of sourcing loop current and for open circuit conditions is about -4V from ground. The ring output is capable of sinking loop current and for open circuit conditions is about VBAT +4V. VF signal transmission is normal. The loop current and ground key detectors are both active, E0 and E1 determine which detector is gated to the DET output.
Thermal Shutdown Protection
The HC5526's thermal shutdown protection is invoked if a fault condition on the tip or ring causes the temperature of the die to exceed 160oC. If this happens, the SLIC goes into a high impedance state and will remain there until the temperature of the die cools down by about 20oC. The SLIC will return back to its normal operating mode, providing the fault condition has been removed.
Ringing State (C1 = 1, C2 = 0)
The ring relay driver and the ring trip detector are activated. Both the tip and ring line drive amplifiers are powered down. Both tip and ring are disconnected from the line via the external ring relay.
Surge Voltage Protection
The HC5526 must be protected against surge voltages and power crosses. Refer to "Maximum Ratings" TIPX and RINGX terminals for maximum allowable transient tip and ring voltages. The protection circuit shown in Figure 21 utilizes diodes together with a clamping device to protect tip and ring against high voltage transients. Positive transients on tip or ring are clamped to within a couple of volts above ground via diodes D1 and D2. Under normal operating conditions D1 and D2 are reverse biased and out of the circuit. Negative transients on tip and ring are clamped to within a couple of volts below ground via diodes D3 and D4 with the help of a Surgector. The Surgector is required to block conduction through diodes D3 and D4 under normal operating conditions and allows negative surges to be returned to system ground. The fuse resistors (RF) serve a dual purpose of being nondestructive power dissipaters during surge and fuses when the line in exposed to a power cross.
Standby State (C1 = 1, C2 = 1)
Both the tip and ring line drive amplifiers are powered down. Internal resistors are connected between tip to ground and ring to VBAT to allow loop current detect in an off-hook condition. The loop current and ground key detectors are both active, E0 and E1 determine which detector is gated to the DET output.
AC Transmission Circuit Stability
To ensure stability of the AC transmission feedback loop two compensation capacitors CTC and CRC are required. Figure 21 (Application Circuit) illustrates their use. Recommended value is 2200pF.
AC-DC Separation Capacitor, CHP
The high pass filter capacitor connected between pins HPT and HPR provides the separation between circuits sensing tip to ring DC conditions and circuits processing AC signals. A 10nf CHP will position the low end frequency response 3dB break point at 48Hz. Where:
1 f 3dB = ---------------------------------------------------( 2 * * R HP * C HP ) (EQ. 28)
where RHP = 330k.
69
HC5526 SLIC Operating States
TABLE 1. LOGIC TRUTH TABLE E0 0 0 0 0 E1 0 0 0 0 C1 0 0 1 1 C2 0 1 0 1 SLIC OPERATING STATE Open Circuit Active Ringing Standby ACTIVE DETECTOR No Active Detector Ground Key Detector No Active Detector Ground Key Detector DET OUTPUT Logic Level High Ground Key Status Logic Level High Ground Key Status
0 0 0 0
1 1 1 1
0 0 1 1
0 1 0 1
Open Circuit Active Ringing Standby
No Active Detector Loop Current Detector Ring Trip Detector Loop Current Detector
Logic Level High Loop Current Status Ring Trip Status Loop Current Status
1 1 1 1
0 0 0 0
0 0 1 1
0 1 0 1
Open Circuit Active Ringing Standby
No Active Detector Ground Key Detector No Active Detector Ground Key Detector
Logic Level High
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
Open Circuit Active Ringing Standby
No Active Detector Loop Current Detector Ring Trip Detector Loop Current Detector 4. Longitudinal Current Limit (Off-Hook Active). Off - Hook (Active, C1 = 1, C2 = 0) longitudinal current limit is determined by increasing the amplitude of EL (Figure 3A) until the 2-wire longitudinal balance drops below 45dB. DET pin remains low (no false detection). 5. Longitudinal Current Limit (On-Hook Standby). On - Hook (Active, C1 = 1, C2 = 1) longitudinal current limit is determined by increasing the amplitude of EL (Figure 3B) until the 2-wire longitudinal balance drops below 45dB. DET pin remains high (no false detection). 6. Longitudinal to Metallic Balance. The longitudinal to metallic balance is computed using the following equation: BLME = 20 * log (EL /VTR), where: EL and VTR are defined in Figure 4. 7. Metallic to Longitudinal FCC Part 68, Para 68.310. The metallic to longitudinal balance is defined in this spec. 8. Longitudinal to Four-Wire Balance. The longitudinal to 4-wire balance is computed using the following equation: BLFE = 20 * log (EL /VTX),: EL and VTX are defined in Figure 4. 9. Metallic to Longitudinal Balance. The metallic to longitudinal balance is computed using the following equation: BMLE = 20 * log (ETR /VL), ERX = 0, where: ETR , VL and ERX are defined in Figure 5. 10. Four-Wire to Longitudinal Balance. The 4-wire to longitudinal balance is computed using the following equation: BFLE = 20 * log (ERX /VL), ETR = source is removed, where: ERX , VL and ETR are defined in Figure 5.
Power-Up Sequence
The HC5526 has no required power-up sequence. This is a result of the Dielectrically Isolated (DI) process used in the fabrication of the part. By using the DI process, care is no longer required to insure that the substrate be kept at the most negative potential as with junction isolated ICs.
Printed Circuit Board Layout
Care in the printed circuit board layout is essential for proper operation. All connections to the RSN pin should be made as close to the device pin as possible, to limit the interference that might be injected into the RSN terminal. It is good practice to surround the RSN pin with a ground plane. The analog and digital grounds should be tied together at the device.
Notes
2. Overload Level (Two-Wire port). The overload level is specified at the 2-wire port (VTR0) with the signal source at the 4-wire receive port (ERX). IDCMET = 30mA, increase the amplitude of ERX until 1% THD is measured at VTRO . Reference Figure 1. 3. Longitudinal Impedance. The longitudinal impedance is computed using the following equations, where TIP and RING voltages are referenced to ground. LZT, LZR , VT, VR , AR and AT are defined in Figure 2. (TIP) LZT = VT /AT, (RING) LZR = VR /AR , where: EL = 1VRMS (0Hz to 100Hz).
70
HC5526
11. Two-Wire Return Loss. The 2-wire return loss is computed using the following equation: r = -20 * log (2VM /VS), where: ZD = The desired impedance; e.g., the characteristic impedance of the line, nominally 600. (Reference Figure 6). 12. Overload Level (4-Wire port). The overload level is specified at the 4-wire transmit port (VTXO) with the signal source (EG) at the 2-wire port, IDCMET = 23mA, ZL = 20k (Reference Figure 7). Increase the amplitude of EG until 1% THD is measured at VTXO. Note that the gain from the 2-wire port to the 4-wire port is equal to 1. 13. Output Offset Voltage. The output offset voltage is specified with the following conditions: EG = 0, IDCMET = 23mA, ZL = and is measured at VTX . EG , IDCMET, VTX and ZL are defined in Figure 7. Note: IDCMET is established with a series 600 resistor between tip and ring. 14. Two-Wire to Four-Wire (Metallic to VTX) Voltage Gain. The 2wire to 4-wire (metallic to VTX) voltage gain is computed using the following equation. G2-4 = (VTX /VTR), EG = 0dBm0, VTX , VTR , and EG are defined in Figure 7. 15. Current Gain RSN to Metallic. The current gain RSN to Metallic is computed using the following equation: K = IM [(RDC1 + RDC2)/(VRDC - VRSN)] VRDC and VRSN are defined in Figure 8. K, IM , RDC1, RDC2 , 20. Four-Wire to Two-Wire Insertion Loss. The 4-wire to 2-wire insertion loss is measured based upon ERX = 0dBm, 1.0kHz input signal, EG = 0, IDCMET = 23mA and is computed using the following equation: L4-2 = 20 * log (VTR /ERX). where: VTR and ERX are defined in Figure 9. 21. Two-Wire to Four-Wire Gain Tracking. The 2-wire to 4-wire gain tracking is referenced to measurements taken for EG = -10dBm, 1.0kHz signal, ERX = 0, IDCMET = 23mA and is computed using the following equation. G2-4 = 20 * log (VTX /VTR) vary amplitude -40dBm to +3dBm, or -55dBm to -40dBm and compare to -10dBm reading. VTX and VTR are defined in Figure 9. 22. Four-Wire to Two-Wire Gain Tracking. The 4-wire to 2-wire gain tracking is referenced to measurements taken for ERX = -10dBm, 1.0kHz signal, EG = 0, IDCMET = 23mA and is computed using the following equation: G4-2 = 20 * log (VTR /ERX) vary amplitude -40dBm to +3dBm, or -55dBm to -40dBm and compare to -10dBm reading. VTR and ERX are defined in Figure 9. The level is specified at the 4-wire receive port and referenced to a 600 impedance level. 23. Two-Wire Idle Channel Noise. The 2-wire idle channel noise at VTR is specified with the 2-wire port terminated in 600 (RL) and with the 4-wire receive port grounded (Reference Figure 10). 24. Four-Wire Idle Channel Noise. The 4-wire idle channel noise at VTX is specified with the 2-wire port terminated in 600 (RL). The noise specification is with respect to a 600 impedance level at VTX. The 4-wire receive port is grounded (Reference Figure 10). 25. Harmonic Distortion (2-Wire to 4-Wire). The harmonic distortion is measured with the following conditions. EG = 0dBm at 1kHz, IDCMET = 23mA. Measurement taken at VTX. (Reference Figure 7). 26. Harmonic Distortion (4-Wire to 2-Wire). The harmonic distortion is measured with the following conditions. ERX = 0dBm0. Vary frequency between 300Hz and 3.4kHz, IDCMET = 23mA. Measurement taken at VTR. (Reference Figure 9). 27. Constant Loop Current. The constant loop current is calculated using the following equation: IL = 2500 / (RDC1 + RDC2). 28. Standby State Loop Current. The standby state loop current is calculated using the following equation: IL = [|VBAT| - 3] / [RL +1800], TA = 25oC. 29. Ground Key Detector. (TRIGGER) Increase the input current to 8mA and verify that DET goes low. (RESET) Decrease the input current from 17mA to 3mA and verify that DET goes high. (Hysteresis) Compare difference between trigger and reset. 30. Power Supply Rejection Ratio. Inject a 100mVRMS signal (50Hz to 4kHz) on VBAT, VCC and VEE supplies. PSRR is computed using the following equation: PSRR = 20 * log (VTX /VIN). VTX and VIN are defined in Figure 12.
16. Two-Wire to Four-Wire Frequency Response. The 2-wire to 4-wire frequency response is measured with respect to EG = 0dBm at 1.0kHz, ERX = 0V, IDCMET = 23mA. The frequency response is computed using the following equation: F2-4 = 20 * log (VTX /VTR), vary frequency from 300Hz to 3.4kHz and compare to 1kHz reading. VTX , VTR , and EG are defined in Figure 9. 17. Four-Wire to Two-Wire Frequency Response. The 4-wire to 2-wire frequency response is measured with respect to ERX = 0dBm at 1.0kHz, EG = 0V, IDCMET = 23mA. The frequency response is computed using the following equation: F4-2 = 20 * log (VTR /ERX), vary frequency from 300Hz to 3.4kHz and compare to 1kHz reading. VTR and ERX are defined in Figure 9. 18. Four-Wire to Four-Wire Frequency Response. The 4-wire to 4-wire frequency response is measured with respect to ERX = 0dBm at 1.0kHz, EG = 0V, IDCMET = 23mA. The frequency response is computed using the following equation: F4-4 = 20 * log (VTX /ERX), vary frequency from 300Hz to 3.4kHz and compare to 1kHz reading. VTX and ERX are defined in Figure 9. 19. Two-Wire to Four-Wire Insertion Loss. The 2-wire to 4-wire insertion loss is measured with respect to EG = 0dBm at 1.0kHz input signal, ERX = 0, IDCMET = 23mA and is computed using the following equation: L2-4 = 20 * log (VTX /VTR). where: VTX , VTR , and EG are defined in Figure 9. (Note: The fuse resistors, RF, impact the insertion loss. The specified insertion loss is for RF = 0).
71
HC5526 Pin Descriptions
PLCC 1 2 4 5 6 7 8 9 11 7 8 9 10 11 12 13 14 PDIP SYMBOL DESCRIPTION RINGSENSE Internally connected to output of RING power amplifier. BGND VCC RINGRLY VBAT RSG E1 E0 DET Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground. Internally separate from AGND but it is recommended that it is connected to the same potential as AGND. 5V power supply. Ring relay driver output. Battery supply voltage, -24V to -56V. Saturation guard programming resistor pin. TTL compatible logic input. The logic state of E1 in conjunction with the logic state of C1 determines which detector is gated to the DET output. TTL compatible logic input. Enables the DET output when set to logic level zero and disables DET output when set to a logic level one. Detector output. TTL compatible logic output. A zero logic level indicates that the selected detector was triggered (see Truth Table for selection of Ground Key detector, Loop Current detector or the Ring Trip detector). The DET output is an open collector with an internal pull-up of approximately 15k to VCC. TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active, Ringing or Standby) of the SLIC. TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active, Ringing or Standby) of the SLIC. DC feed current programming resistor pin. Constant current feed is programmed by resistors RDC1 and RDC2 connected in series from this pin to the receive summing node (RSN). The resistor junction point is decoupled to AGND to isolate the AC signal components. Analog ground. Receive Summing Node. The AC and DC current flowing into this pin establishes the metallic loop current that flows between tip and ring. The magnitude of the metallic loop current is 1000 times greater than the current into the RSN pin. The constant current programming resistors and the networks for program receive gain and 2-wire impedance all connect to this pin. -5V power supply. Transmit audio output. This output is equivalent to the TIP to RING metallic voltage. The network for programming the 2-wire input impedance connects between this pin and RSN. RING side of AC/DC separation capacitor CHP. CHP is required to properly separate the ring AC current from the DC loop current. The other end of CHP is connected to HPT. TIP side of AC/DC separation capacitor CHP. CHP is required to properly separate the tip AC current from the DC loop current. The other end of CHP is connected to HPR. Loop current programming resistor. Resistor RD sets the trigger level for the loop current detect circuit. A filter capacitor CD is also connected between this pin and VEE. Input to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a comparator in the SLIC with inputs DT and DR. Input to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a comparator in the SLIC with inputs DT and DR. Internally connected to output of tip power amplifier. Output of tip power amplifier. Output of ring power amplifier. No internal connection.
12 13 14
15 16 17
C2 C1 RDC
15 16
18 19
AGND RSN
18 19 20 21 22 23 25 26 27 28 3, 10, 17, 24
20 21 22 1 2 3 4
VEE VTX HPR HPT RD DT DR TIPSENSE
5 6
TIPX RINGX N/C
72
HC5526 Pinouts
HC5526 (PLCC) TOP VIEW
RINGSENSE TIPSENSE HPT RD DT DR TIPX RINGRLY 5 25 DR 24 N/C 23 DT 22 RD 21 HPT 20 HPR 19 VTX RINGX BGND 1 2 3 4 5 6 7
HC5526 (PDIP) TOP VIEW
22 HPR 21 VTX 20 VEE 19 RSN 18 AGND 17 RDC 16 C1 15 C2 14 DET 13 E0 12 E1
BGND
RINGX 28
4
3
2
1
27
TIPX
VCC
N/C
26
VBAT 6 RSG 7 E1 E0 8 9
VCC 8 RINGRLY 9
VBAT 10 RSG 11
N/C 10 DET 11
12 C2
13 C1
14 RDC
15 AGND
16 RSN
17 N/C
18 VEE
73
HC5526 Application Circuit
RRT R3
CRT
R1 RD 21 HPT
CHP (NOTE 32) RFB U1 HPR 20 RTX VTX 19 VEE 18 RSN 16 AGND 15 RDC 14 RDC2 CRC D2 28 RINGX C2 12 DET 11 EO 9 E1 8 4 VCC C1 13 CDC RDC1 CODEC/FILTER 2 BGND -5V RT RB RRX U2 +
R4
R2
-5V 22 RD
-
VBAT PTC TIP PTC RING D4 RF2 RF1 D3 NOTE 31 D1 CTC
23 DT 25 DR 27 TIPX
Surgector
K G A
VBAT 6 VBAT 5 RINGRLY RSG 7 RSG
D5 RINGING (VBAT + 90VRMS) +5V OR 12V RELAY
-5V
D6
U1 SLIC (Subscriber Line Interface Circuit) HC5526 U2 Combination CODEC/Filter e.g. CD22354A or Programmable CODEC/ Filter, e.g. SLAC CDC 1.5F, 20%, 10V CHP 10nF, 20%, 100V (Note 2) CRT 0.39F, 20%, 100V CTC, CRC 2200pF, 20%, 100V Relay Relay, 2C Contacts, 5V or 12V Coil D1 - D5 MOR120 Diode Surgector SGT27S10 PTC Polyswitch TR600-150 D6 Diode, 1N4454
RF1, RF2 Line Resistor, 20, 1% Match, 2 W Carbon column resistor or thick film on ceramic R1, R3 200k, 5%, 1/4W R2 910k, 5%, 1/4W R4 1.2M, 5%, 1/4W RB 18.7k,1%, 1/4W RD 39k, 5%, 1/4W RDC1, RDC2 41.2k, 5%, 1/4W RFB 20.0k, 1%, 1/4W RRX 280k, 1%, 1/4W RT 562k, 1%, 1/4W RTX 20k, 1%, 1/4W RRT 150, 5%, 2W RSG VBAT = -28V, RSG = VBAT = -48V, RSG = 21.4k, 1/4W 5%
NOTES: 31. It is recommended that the anodes of D3 and D4 be shorted to ground through a battery referenced surgector (SGT27S10). 32. To meet the specified 25dB 2-wire return loss at 200Hz, CHP needs to be 20nF, 20%, 100V. FIGURE 21. APPLICATION CIRCUIT
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